Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation

Andres Malavasi-Mora; Renato Rimolo-Donadio

doi:10.1109/LASCAS45839.2020.9069016

Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation

Andres Malavasi-Mora, Renato Rimolo-Donadio

Escuela de Ingeniería Electrónica

Intel

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

Resumen

High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. A guard band needs to be set in order to tolerate voltage drops without having any execution problem but leading to a performance reduction. This work proposes a technique to enhance voltage drop tolerance through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated with test cases in a FinFet CMOS technology at a post-layout simulation level, reaching from 6% up to 30% more voltage drop tolerance.

Idioma original	Inglés
Título de la publicación alojada	2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
Editorial	Institute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)	9781728134277
DOI	https://doi.org/10.1109/LASCAS45839.2020.9069016
Estado	Publicada - feb 2020
Evento	11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 - San Jose, Costa Rica Duración: 25 feb 2020 → 28 feb 2020

Serie de la publicación

Nombre	2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

Conferencia

Conferencia	11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
País/Territorio	Costa Rica
Ciudad	San Jose
Período	25/02/20 → 28/02/20

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10.1109/LASCAS45839.2020.9069016

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Malavasi-Mora, A., & Rimolo-Donadio, R. (2020). Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation. En 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020 Artículo 9069016 (2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS45839.2020.9069016

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abstract = "High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. A guard band needs to be set in order to tolerate voltage drops without having any execution problem but leading to a performance reduction. This work proposes a technique to enhance voltage drop tolerance through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated with test cases in a FinFet CMOS technology at a post-layout simulation level, reaching from 6% up to 30% more voltage drop tolerance.",

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Malavasi-Mora, A & Rimolo-Donadio, R 2020, Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation. En 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020., 9069016, 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020, Institute of Electrical and Electronics Engineers Inc., 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020, San Jose, Costa Rica, 25/02/20. https://doi.org/10.1109/LASCAS45839.2020.9069016

Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation. / Malavasi-Mora, Andres; Rimolo-Donadio, Renato.
2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9069016 (2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

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N2 - High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. A guard band needs to be set in order to tolerate voltage drops without having any execution problem but leading to a performance reduction. This work proposes a technique to enhance voltage drop tolerance through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated with test cases in a FinFet CMOS technology at a post-layout simulation level, reaching from 6% up to 30% more voltage drop tolerance.

AB - High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. A guard band needs to be set in order to tolerate voltage drops without having any execution problem but leading to a performance reduction. This work proposes a technique to enhance voltage drop tolerance through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated with test cases in a FinFet CMOS technology at a post-layout simulation level, reaching from 6% up to 30% more voltage drop tolerance.

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KW - clock-data compensation

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KW - power noise

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BT - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

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Malavasi-Mora A, Rimolo-Donadio R. Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation. En 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9069016. (2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020). doi: 10.1109/LASCAS45839.2020.9069016

Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation

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