TY - GEN
T1 - Terabit/s packaging design for testing of high-speed IC transceivers
AU - Baks, Christian
AU - Rimolo-Donadio, Renato
AU - Kwark, Young H.
AU - Doany, Fuad E.
AU - Gu, Xiaoxiong
AU - Kuchta, Daniel M.
AU - Lee, Benjamin G.
AU - Rylyakov, Alexander V.
AU - Libsch, Frank
AU - Schow, Clint L.
PY - 2013
Y1 - 2013
N2 - An electrical packaging platform to support the testing of high-speed IC transceivers with aggregate data rates up to 0.48 Tb/s Tx + 0.48 Tb/s Rx (24 transmitters and 24 receivers up to 20 Gb/s per channel) is presented. The design requirements, potential solutions, and considerations for a successful implementation are discussed together with the characterization and evaluation of a passive interconnect system that spans package, board, and high-speed connectors. This platform is used to demonstrate the operation of VCSEL-based optoelectronic buses for short-reach applications relying on a custom IBM CMOS "holey" optochip.
AB - An electrical packaging platform to support the testing of high-speed IC transceivers with aggregate data rates up to 0.48 Tb/s Tx + 0.48 Tb/s Rx (24 transmitters and 24 receivers up to 20 Gb/s per channel) is presented. The design requirements, potential solutions, and considerations for a successful implementation are discussed together with the characterization and evaluation of a passive interconnect system that spans package, board, and high-speed connectors. This platform is used to demonstrate the operation of VCSEL-based optoelectronic buses for short-reach applications relying on a custom IBM CMOS "holey" optochip.
UR - http://www.scopus.com/inward/record.url?scp=84883701140&partnerID=8YFLogxK
M3 - Contribución a la conferencia
AN - SCOPUS:84883701140
SN - 9781627484725
T3 - DesignCon 2013: Where Chipheads Connect
SP - 1786
EP - 1806
BT - DesignCon 2013
T2 - DesignCon 2013: Where Chipheads Connect
Y2 - 28 January 2013 through 31 January 2013
ER -