TY - GEN
T1 - Signal and power integrity (SPI) co-analysis for high-speed communication channels
AU - Rimolo-Donadio, Renato
AU - Duan, Xiaomin
AU - Kwark, Young H.
AU - Gu, Xiaoxiong
AU - Baks, Christian W.
AU - Müller, Sebastian
AU - Winkel, Thomas Michael
AU - Strach, Thomas
AU - Shan, Lei
AU - Harrer, Hubert
AU - Schuster, Christian
PY - 2013
Y1 - 2013
N2 - The modeling of multiple high-speed chip-to-chip communication links over first (IC package) and second (board) level interconnects is addressed in this paper for data rates up to 28 Gb/s with model-to-hardware correlation. The suggested methodology is based on a bottom-up hybrid approach combining semi-analytical and numerical models, which are able to simultaneously consider the signal and power integrity domains and allow the incorporation of power noise models for the time domain link simulation. The required model complexity and the design space for passive interconnects are explored by analyzing diverse via and channel configurations.
AB - The modeling of multiple high-speed chip-to-chip communication links over first (IC package) and second (board) level interconnects is addressed in this paper for data rates up to 28 Gb/s with model-to-hardware correlation. The suggested methodology is based on a bottom-up hybrid approach combining semi-analytical and numerical models, which are able to simultaneously consider the signal and power integrity domains and allow the incorporation of power noise models for the time domain link simulation. The required model complexity and the design space for passive interconnects are explored by analyzing diverse via and channel configurations.
UR - http://www.scopus.com/inward/record.url?scp=84883713987&partnerID=8YFLogxK
M3 - Contribución a la conferencia
AN - SCOPUS:84883713987
SN - 9781627484725
T3 - DesignCon 2013: Where Chipheads Connect
SP - 807
EP - 831
BT - DesignCon 2013
T2 - DesignCon 2013: Where Chipheads Connect
Y2 - 28 January 2013 through 31 January 2013
ER -