TY - GEN
T1 - Review of CMOS circuit architectures for Electrical Impedance Spectroscopy
AU - Garcia-Ramirez, Ronny
AU - Villalta-Gutierrez, Oscar
AU - Rimolo-Donadio, Renato
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/2
Y1 - 2016/7/2
N2 - In this paper, different architectures at integrated circuit level for the implementation of Electrical Impedance Spectroscopy(EIS) systems are compared and discused. The main functional blocks required by each architecture and their underlying concepts are explained. Additionally, the performance and design specifications for different implementations are contrasted.
AB - In this paper, different architectures at integrated circuit level for the implementation of Electrical Impedance Spectroscopy(EIS) systems are compared and discused. The main functional blocks required by each architecture and their underlying concepts are explained. Additionally, the performance and design specifications for different implementations are contrasted.
KW - Broadband Impedance Spectroscopy
KW - CMOS Circuits
KW - Electric Impedance Spectroscopy
KW - Impedance
KW - Spectroscopy
UR - http://www.scopus.com/inward/record.url?scp=85021456910&partnerID=8YFLogxK
U2 - 10.1109/CONCAPAN.2016.7942355
DO - 10.1109/CONCAPAN.2016.7942355
M3 - Contribución a la conferencia
AN - SCOPUS:85021456910
T3 - 2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016
BT - 2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 36th IEEE Central American and Panama Convention, CONCAPAN 2016
Y2 - 9 November 2016 through 11 November 2016
ER -