TY - GEN
T1 - Prototyping a Biologically Plausible Neuron Model on a Heterogeneous CPU-FPGA Board
AU - Alfaro-Badilla, Kaleb
AU - Chacon-Rodriguez, Alfonso
AU - Smaragdos, Georgios
AU - Strydis, Christos
AU - Arroyo-Romero, Andres
AU - Espinoza-Gonzalez, Javier
AU - Salazar-Garcia, Carlos
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/3/14
Y1 - 2019/3/14
N2 - A heterogeneous hardware-software system implemented on an Avnet ZedBoard Zynq SoC platform, is proposed for the computation of an extended Hodgkin Huxley (eHH), biologically plausible neural model. SoC's ARM A9 is in charge of handling execution of a single neuron as defined in the eHH model, each with a O(N) computational complexity, while the computation of the gap-junctions interactions for each cell is offloaded on the SoC's FPGA, cutting its O(N2) complexity by exploiting parallel-computing hardware techniques. The proposed hw-sw solution allows for speed-ups of about 18 times visa-vis à vectorized software implementation on the SoC's cores, and is comparable to the speed of the same model optimized for a 64-bit Intel Quad Core i7, at 3.9GHz.
AB - A heterogeneous hardware-software system implemented on an Avnet ZedBoard Zynq SoC platform, is proposed for the computation of an extended Hodgkin Huxley (eHH), biologically plausible neural model. SoC's ARM A9 is in charge of handling execution of a single neuron as defined in the eHH model, each with a O(N) computational complexity, while the computation of the gap-junctions interactions for each cell is offloaded on the SoC's FPGA, cutting its O(N2) complexity by exploiting parallel-computing hardware techniques. The proposed hw-sw solution allows for speed-ups of about 18 times visa-vis à vectorized software implementation on the SoC's cores, and is comparable to the speed of the same model optimized for a 64-bit Intel Quad Core i7, at 3.9GHz.
KW - Biologically accurate neural networks models
KW - hardware-software co-design
KW - heterogeneous systems
KW - high level synthesis
KW - spiking neural networks
KW - systems on chip
UR - http://www.scopus.com/inward/record.url?scp=85064169900&partnerID=8YFLogxK
U2 - 10.1109/LASCAS.2019.8667538
DO - 10.1109/LASCAS.2019.8667538
M3 - Contribución a la conferencia
AN - SCOPUS:85064169900
T3 - 2019 IEEE 10th Latin American Symposium on Circuits and Systems, LASCAS 2019 - Proceedings
SP - 5
EP - 8
BT - 2019 IEEE 10th Latin American Symposium on Circuits and Systems, LASCAS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 10th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2019
Y2 - 24 February 2019 through 27 February 2019
ER -