TY - GEN
T1 - Improving the Simulation of Biologically Accurate Neural Networks Using Data Flow HLS Transformations on Heterogeneous SoC-FPGA Platforms
AU - Alfaro-Badilla, Kaleb
AU - Arroyo-Romero, Andrés
AU - Salazar-García, Carlos
AU - León-Vega, Luis G.
AU - Espinoza-González, Javier
AU - Hernández-Castro, Franklin
AU - Chacón-Rodríguez, Alfonso
AU - Smaragdos, Georgios
AU - Strydis, Christos
N1 - Publisher Copyright:
© 2020, Springer Nature Switzerland AG.
PY - 2020
Y1 - 2020
N2 - This work proposes a hardware performance-oriented design methodology aimed at generating efficient high-level synthesis (HLS) coded data multiprocessing on a heterogeneous platform. The methodology is tested on typical neuroscientific complex application: the biologically accurate modeling of a brain region known as the inferior olivary nucleus (ION). The ION cells are described using a multi-compartmental model based on the extended Hodgkin-Huxley membrane model (eHH), which requires the solution of a set of coupled differential equations. The proposed methodology is tested against alternative HPC implementations (multi-core CPU i7-7820HQ, and a Virtex7 FPGA) of the same ION model for different neural network sizes. Results show that the solution runs 10 to 4 times faster than our previous implementation using the same board and closes the gap between the performance against a Virtex7 implementation without using at full-capacity the AXI-HP channels.
AB - This work proposes a hardware performance-oriented design methodology aimed at generating efficient high-level synthesis (HLS) coded data multiprocessing on a heterogeneous platform. The methodology is tested on typical neuroscientific complex application: the biologically accurate modeling of a brain region known as the inferior olivary nucleus (ION). The ION cells are described using a multi-compartmental model based on the extended Hodgkin-Huxley membrane model (eHH), which requires the solution of a set of coupled differential equations. The proposed methodology is tested against alternative HPC implementations (multi-core CPU i7-7820HQ, and a Virtex7 FPGA) of the same ION model for different neural network sizes. Results show that the solution runs 10 to 4 times faster than our previous implementation using the same board and closes the gap between the performance against a Virtex7 implementation without using at full-capacity the AXI-HP channels.
KW - Dataflow
KW - FPGA
KW - HLS
KW - HPC
KW - Inferior olivary nucleus
KW - Spiking neural networks
UR - http://www.scopus.com/inward/record.url?scp=85081170196&partnerID=8YFLogxK
U2 - 10.1007/978-3-030-41005-6_13
DO - 10.1007/978-3-030-41005-6_13
M3 - Contribución a la conferencia
AN - SCOPUS:85081170196
SN - 9783030410049
T3 - Communications in Computer and Information Science
SP - 185
EP - 199
BT - High Performance Computing - 6th Latin American Conference, CARLA 2019, Revised Selected Papers
A2 - Crespo-Mariño, Juan Luis
A2 - Meneses-Rojas, Esteban
PB - Springer
T2 - 6th Latin American High Performance Computing Conference, CARLA 2019
Y2 - 25 September 2019 through 27 September 2019
ER -