Implementation of an open core IEEE 754-based FPU with non-linear arithmetic support

Adrian Cervantes; Francis Lopez; Jeffry Quiros; Diego Rodriguez; Carlos Salazar-Garcia; Carlos Meza; Alfonso Chacon-Rodriguez

doi:10.1109/CONCAPAN.2016.7942354

Implementation of an open core IEEE 754-based FPU with non-linear arithmetic support

Adrian Cervantes, Francis Lopez, Jeffry Quiros, Diego Rodriguez, Carlos Salazar-Garcia, Carlos Meza, Alfonso Chacon-Rodriguez

Costa Rica Institute of Technology

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

Resumen

FPGA implementation results of an open core IEEE 754-based FPU with non-linear arithmetic support are shown. Non-linear operations are implemented using variations of the CORDIC algorithm, and are tested on a commercial FPGA. The unit provides results both on 32-bit and 64-bit FPU formats, with error bounded to 0.81501% for the cosine operation, 0.91367% for the sine operation, and 0.129% for the natural logarithm operation, using sixteen iterations in all cases, and a 64-bit floating point representation. Dynamic power is under 11mW for each non-linear operational block, at a 100MHz clock speed.

Idioma original	Inglés
Título de la publicación alojada	2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016
Editorial	Institute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)	9781467395786
DOI	https://doi.org/10.1109/CONCAPAN.2016.7942354
Estado	Publicada - 2 jul 2016
Evento	36th IEEE Central American and Panama Convention, CONCAPAN 2016 - San Jose, Costa Rica Duración: 9 nov 2016 → 11 nov 2016

Serie de la publicación

Nombre	2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016

Conferencia

Conferencia	36th IEEE Central American and Panama Convention, CONCAPAN 2016
País/Territorio	Costa Rica
Ciudad	San Jose
Período	9/11/16 → 11/11/16

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10.1109/CONCAPAN.2016.7942354

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Cervantes, A., Lopez, F., Quiros, J., Rodriguez, D., Salazar-Garcia, C., Meza, C., & Chacon-Rodriguez, A. (2016). Implementation of an open core IEEE 754-based FPU with non-linear arithmetic support. En 2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016 Artículo 7942354 (2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CONCAPAN.2016.7942354

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abstract = "FPGA implementation results of an open core IEEE 754-based FPU with non-linear arithmetic support are shown. Non-linear operations are implemented using variations of the CORDIC algorithm, and are tested on a commercial FPGA. The unit provides results both on 32-bit and 64-bit FPU formats, with error bounded to 0.81501% for the cosine operation, 0.91367% for the sine operation, and 0.129% for the natural logarithm operation, using sixteen iterations in all cases, and a 64-bit floating point representation. Dynamic power is under 11mW for each non-linear operational block, at a 100MHz clock speed.",

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Cervantes, A, Lopez, F, Quiros, J, Rodriguez, D, Salazar-Garcia, C , Meza, C & Chacon-Rodriguez, A 2016, Implementation of an open core IEEE 754-based FPU with non-linear arithmetic support. En 2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016., 7942354, 2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016, Institute of Electrical and Electronics Engineers Inc., 36th IEEE Central American and Panama Convention, CONCAPAN 2016, San Jose, Costa Rica, 9/11/16. https://doi.org/10.1109/CONCAPAN.2016.7942354

Implementation of an open core IEEE 754-based FPU with non-linear arithmetic support. / Cervantes, Adrian; Lopez, Francis; Quiros, Jeffry et al.
2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7942354 (2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

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AU - Chacon-Rodriguez, Alfonso

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AB - FPGA implementation results of an open core IEEE 754-based FPU with non-linear arithmetic support are shown. Non-linear operations are implemented using variations of the CORDIC algorithm, and are tested on a commercial FPGA. The unit provides results both on 32-bit and 64-bit FPU formats, with error bounded to 0.81501% for the cosine operation, 0.91367% for the sine operation, and 0.129% for the natural logarithm operation, using sixteen iterations in all cases, and a 64-bit floating point representation. Dynamic power is under 11mW for each non-linear operational block, at a 100MHz clock speed.

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Cervantes A, Lopez F, Quiros J, Rodriguez D, Salazar-Garcia C , Meza C et al. Implementation of an open core IEEE 754-based FPU with non-linear arithmetic support. En 2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7942354. (2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016). doi: 10.1109/CONCAPAN.2016.7942354

Implementation of an open core IEEE 754-based FPU with non-linear arithmetic support

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