TY - GEN
T1 - Fully analytical methodology for fast end-to-end link analysis on complex printed circuit boards including signal and power integrity effects
AU - Gu, Xiaoxiong
AU - De Paulis, Francesco
AU - Rimolo-Donadio, Renato
AU - Shringarpure, Ketan
AU - Zhang, Yaojiang
AU - Archambeault, Bruce
AU - Connor, Sam
AU - Kwark, Young H.
AU - Ritter, Mark B.
AU - Fan, Jun
AU - Schuster, Christian
PY - 2009
Y1 - 2009
N2 - High speed printed circuit boards (PCBs) can be extremely complex with a large number of via structures and transmission lines. Rapid analysis of on-board high speed nets including the non-TEM effects of vias with full-wave electromagnetic field solvers has been unrealistic. However, using a systematic, cascaded analytical approach, these high speed nets can now be analyzed quick enough to do design discovery and optimization during the pre-layout phase. The self assembly of the cascaded link path, using analytical models for each individual portion, allows this analysis to be performed in very short time, replacing the time consuming traditional full wave simulation techniques without sacrificing accuracy.
AB - High speed printed circuit boards (PCBs) can be extremely complex with a large number of via structures and transmission lines. Rapid analysis of on-board high speed nets including the non-TEM effects of vias with full-wave electromagnetic field solvers has been unrealistic. However, using a systematic, cascaded analytical approach, these high speed nets can now be analyzed quick enough to do design discovery and optimization during the pre-layout phase. The self assembly of the cascaded link path, using analytical models for each individual portion, allows this analysis to be performed in very short time, replacing the time consuming traditional full wave simulation techniques without sacrificing accuracy.
UR - http://www.scopus.com/inward/record.url?scp=84866400847&partnerID=8YFLogxK
M3 - Contribución a la conferencia
AN - SCOPUS:84866400847
SN - 9781615670499
T3 - Designcon 2009
SP - 1450
EP - 1467
BT - Designcon 2009
T2 - Designcon 2009
Y2 - 2 February 2009 through 5 February 2009
ER -