Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products

The high-performance microprocessor industry is moving towards the paradigm of heterogeneously integrated IC products, as an alternative to offer more customizable solutions to different market segments at a more rapid pace. This approach involves the use of many dice in combination with advanced 2.5 and 3D packaging technologies, where the continuous scaling-down of silicon processes imposes new challenges in terms of process control and assembly reliability. This translates to new test requirements and methods to handle the parallel-massive IO interfaces that are needed to communicate across all dice. In this paper, we review the main approaches and considerations for testing embedded interfaces over silicon bridges in high-volume environments. The Wafer Level Test phase and Final Package Test are discussed, together with the strategies to differentiate silicon and assembly induced fails, repair capabilities, and system margin validation features. Finally, an overview of future challenges for next generation products is provided.