TY - GEN
T1 - AxRSU
T2 - 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
AU - Da Rosa, Morgana M.A.
AU - Paim, Guilherme
AU - Castro-Godinez, Jorge
AU - Da Costa, Eduardo A.C.
AU - Soares, Rafael I.
AU - Bampi, Sergio
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Approximate computing emerged as a design alternative to boost design efficiency by leveraging the intrinsic error resiliency of many applications. Several error-resilient and compute-intensive applications such as signal, image, and video processing, computer vision, and supervised machine learning perform mean squared error (MSE) estimation during the runtime demanding dedicated squarer logic units in their hardware accelerators. This work proposes an approximate Radix-4 squarer unit architecture (AxRSU). Our AxRSU proposal reduces the encoder complexity and the number of required partial products, which considerably boosts energy and circuit area savings. We demonstrate the AxRSU error-quality trade-off in an SSD (Sum Squared Difference) hardware accelerator as a case study targeting a video processing application. We offer a new Pareto front with eighth optimal AxRSU solutions ranging 52-97% of cross-correlation (i.e., accuracy) for savings of 15-47% in energy consumption and 12-32% in circuit area.
AB - Approximate computing emerged as a design alternative to boost design efficiency by leveraging the intrinsic error resiliency of many applications. Several error-resilient and compute-intensive applications such as signal, image, and video processing, computer vision, and supervised machine learning perform mean squared error (MSE) estimation during the runtime demanding dedicated squarer logic units in their hardware accelerators. This work proposes an approximate Radix-4 squarer unit architecture (AxRSU). Our AxRSU proposal reduces the encoder complexity and the number of required partial products, which considerably boosts energy and circuit area savings. We demonstrate the AxRSU error-quality trade-off in an SSD (Sum Squared Difference) hardware accelerator as a case study targeting a video processing application. We offer a new Pareto front with eighth optimal AxRSU solutions ranging 52-97% of cross-correlation (i.e., accuracy) for savings of 15-47% in energy consumption and 12-32% in circuit area.
KW - Approximate Computing
KW - Approximate Squarer Unit
KW - Radix-4 Squarer Unit
KW - VLSI Hardware Design
UR - http://www.scopus.com/inward/record.url?scp=85137719013&partnerID=8YFLogxK
U2 - 10.1109/ISCAS48785.2022.9937770
DO - 10.1109/ISCAS48785.2022.9937770
M3 - Contribución a la conferencia
AN - SCOPUS:85137719013
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1655
EP - 1659
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 27 May 2022 through 1 June 2022
ER -