TY - JOUR
T1 - AxHLS
T2 - 39th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2020
AU - Castro-Godinez, Jorge
AU - Mateus-Vargas, Julian
AU - Shafique, Muhammad
AU - Henkel, Jorg
N1 - Publisher Copyright:
© 2020 Association on Computer Machinery.
PY - 2020/11/2
Y1 - 2020/11/2
N2 - With the emergence of approximate computing as a design paradigm, many approximate functional units have been proposed, particularly approximate adders and multipliers. These circuits compromise the accuracy of their results within a tolerable limit to reduce the required computational effort and energy requirements. However, for an ongoing number of such approximate circuits reported in the literature, selecting those that minimize the required resources for designing and generating an approximate accelerator from a high-level specification, while satisfying a defined accuracy constraint, is a joint high-level synthesis (HLS) and design space exploration (DSE) challenge. In this paper, we propose a novel automated framework for HLS of approximate accelerators using a given library of approximate functional units. Since repetitive circuit synthesis and gate-level simulations require a significant amount of time, to enable our framework, we present AxME, a set of analytical models for estimating the required computational resources when using approximate adders and multipliers in approximate designs. We propose DSEwam, a DSE methodology for error-tolerant applications, in which analytical models, such as AxME, are used to estimate resources needed and the accuracy of approximate designs. Furthermore, we integrate DSEwam into an HLS tool to automatically generate Pareto-optimal, or near Pareto-optimal, approximate accelerators from C language descriptions, for a given error threshold and minimization goal. We release our DSE framework as an open-source contribution, which will significantly boost the research and development in the field of automatic generation of approximate accelerators.
AB - With the emergence of approximate computing as a design paradigm, many approximate functional units have been proposed, particularly approximate adders and multipliers. These circuits compromise the accuracy of their results within a tolerable limit to reduce the required computational effort and energy requirements. However, for an ongoing number of such approximate circuits reported in the literature, selecting those that minimize the required resources for designing and generating an approximate accelerator from a high-level specification, while satisfying a defined accuracy constraint, is a joint high-level synthesis (HLS) and design space exploration (DSE) challenge. In this paper, we propose a novel automated framework for HLS of approximate accelerators using a given library of approximate functional units. Since repetitive circuit synthesis and gate-level simulations require a significant amount of time, to enable our framework, we present AxME, a set of analytical models for estimating the required computational resources when using approximate adders and multipliers in approximate designs. We propose DSEwam, a DSE methodology for error-tolerant applications, in which analytical models, such as AxME, are used to estimate resources needed and the accuracy of approximate designs. Furthermore, we integrate DSEwam into an HLS tool to automatically generate Pareto-optimal, or near Pareto-optimal, approximate accelerators from C language descriptions, for a given error threshold and minimization goal. We release our DSE framework as an open-source contribution, which will significantly boost the research and development in the field of automatic generation of approximate accelerators.
KW - analytical models
KW - Approximate computing
KW - design automation
KW - design-space exploration
KW - high-level synthesis
UR - http://www.scopus.com/inward/record.url?scp=85097946323&partnerID=8YFLogxK
U2 - 10.1145/3400302.3415732
DO - 10.1145/3400302.3415732
M3 - Artículo de la conferencia
AN - SCOPUS:85097946323
SN - 1092-3152
VL - 2020-November
JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
M1 - 9256645
Y2 - 2 November 2020 through 5 November 2020
ER -