TY - GEN
T1 - A User-Friendly Ecosystem for AI FPGA-Based Accelerators
AU - Leon-Vega, Luis G.
AU - Obregon-Fonseca, Erick
AU - Castro-Godinez, Jorge
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - The introduction of FPGAs in High-Performance Embedded Computing and Artificial Intelligence still faces chal-enges regarding the difficulty of getting started. It requires hardware knowledge, familiarity with multiple tooling, libraries and frameworks and long synthesis times. To encourage the usage of FPGAs, this work proposes an ecosystem that includes a library with a set of pre-built accelerators for common Digital Signal Processing and Artificial Intelligence workloads, an engine for runtime arbitrary-precision quantisation and an agnostic API, allowing the development of FPGA-accelerated user applications while abstracting the details about the FPGA design and implementation. Our approach is based on hardware reuse, introducing software resource management of a series of pre-built IP cores, allowing low-end FPGAs to be used as hardware accelerators and multiple applications to share resources. Our work is better than managed FPGA standalone applications with Vitis HLS-based quantisation, accelerating 1.22 x, thanks to our quantisation engine, which accelerates 5.12 x the quantisation and 13.30 x the de-quantisation, while keeping close the accelerator execution times.
AB - The introduction of FPGAs in High-Performance Embedded Computing and Artificial Intelligence still faces chal-enges regarding the difficulty of getting started. It requires hardware knowledge, familiarity with multiple tooling, libraries and frameworks and long synthesis times. To encourage the usage of FPGAs, this work proposes an ecosystem that includes a library with a set of pre-built accelerators for common Digital Signal Processing and Artificial Intelligence workloads, an engine for runtime arbitrary-precision quantisation and an agnostic API, allowing the development of FPGA-accelerated user applications while abstracting the details about the FPGA design and implementation. Our approach is based on hardware reuse, introducing software resource management of a series of pre-built IP cores, allowing low-end FPGAs to be used as hardware accelerators and multiple applications to share resources. Our work is better than managed FPGA standalone applications with Vitis HLS-based quantisation, accelerating 1.22 x, thanks to our quantisation engine, which accelerates 5.12 x the quantisation and 13.30 x the de-quantisation, while keeping close the accelerator execution times.
KW - Cloud Computing
KW - Edge Computing
KW - Field Programmable Gate Arrays
KW - Hardware Acceleration
KW - High Performance Computing
UR - http://www.scopus.com/inward/record.url?scp=85202514919&partnerID=8YFLogxK
U2 - 10.1109/COINS61597.2024.10622147
DO - 10.1109/COINS61597.2024.10622147
M3 - Contribución a la conferencia
AN - SCOPUS:85202514919
T3 - 2024 IEEE International Conference on Omni-Layer Intelligent Systems, COINS 2024
BT - 2024 IEEE International Conference on Omni-Layer Intelligent Systems, COINS 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE International Conference on Omni-Layer Intelligent Systems, COINS 2024
Y2 - 29 July 2024 through 31 July 2024
ER -