TY - GEN
T1 - A Novel Proposal for a Standalone Compressor and Decompressor Hardware Module from ISA
AU - Sanabria-Villalobos, Esteban A.
AU - Chavarria-Zamora, Luis A.
AU - Araya-Martinez, Leonardo
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Rapidly evolving markets and growing demand of digital application by consumers, along with hardware long time-to-market and rising manufacturing costs, are pushing the market towards software-based development, directly increasing power, area and memory requirements of current computer systems. Efforts to reduce this growing demand on storage devices are multiple, among them are assembly code compression and decompression techniques, which reduce the memory footprint of programs, thus reducing the resources and costs necessary for their elaboration. For this reason, is proposed a digital design and implementation of a real-time assembly code decompression module, that works under the demand of a processor, which is independent of the ISA, does not require modifications of the processing systems and reduce the amount of memory needed. The proposed microarchitecture is capable of decompress code in real-time, as well the results of the evaluation of the module, consisting of a 32-bit ARM processor and memory holding the compressed instructions, show the adaptability of the module to different ISA and processors using just their common inputs and outputs.
AB - Rapidly evolving markets and growing demand of digital application by consumers, along with hardware long time-to-market and rising manufacturing costs, are pushing the market towards software-based development, directly increasing power, area and memory requirements of current computer systems. Efforts to reduce this growing demand on storage devices are multiple, among them are assembly code compression and decompression techniques, which reduce the memory footprint of programs, thus reducing the resources and costs necessary for their elaboration. For this reason, is proposed a digital design and implementation of a real-time assembly code decompression module, that works under the demand of a processor, which is independent of the ISA, does not require modifications of the processing systems and reduce the amount of memory needed. The proposed microarchitecture is capable of decompress code in real-time, as well the results of the evaluation of the module, consisting of a 32-bit ARM processor and memory holding the compressed instructions, show the adaptability of the module to different ISA and processors using just their common inputs and outputs.
KW - ARM
KW - code compression
KW - design
KW - dictionary compression
KW - DSP
KW - HDL
KW - real-time decompression
KW - Sequitur algorithm
KW - validation
KW - verification
UR - http://www.scopus.com/inward/record.url?scp=85141394353&partnerID=8YFLogxK
U2 - 10.1109/LAEDC54796.2022.9907767
DO - 10.1109/LAEDC54796.2022.9907767
M3 - Contribución a la conferencia
AN - SCOPUS:85141394353
T3 - 2022 IEEE Latin America Electron Devices Conference, LAEDC 2022
BT - 2022 IEEE Latin America Electron Devices Conference, LAEDC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Latin America Electron Devices Conference, LAEDC 2022
Y2 - 4 July 2022 through 6 July 2022
ER -