A comparison of low power architectures for digital delay measurement

Franco Martin-Pirchio; Alfonso Chacón-Rodríguez; Pedro Julián; Pablo Mandolesi

doi:10.1109/ISVLSI.2007.3

A comparison of low power architectures for digital delay measurement

Franco Martin-Pirchio, Alfonso Chacón-Rodríguez, Pedro Julián, Pablo Mandolesi

Escuela de Ingeniería Electrónica

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

Resumen

Two different versions of a method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz are compared in terms of their power dissipation. Power dissipation simulations are run on both versions from their layout on a 0.35μm technology. The second version shows a cut of 37% in total dissipation under the same test conditions.

Idioma original	Inglés
Título de la publicación alojada	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtítulo de la publicación alojada	Emerging VLSI Technologies and Architectures
Páginas	498-499
Número de páginas	2
DOI	https://doi.org/10.1109/ISVLSI.2007.3
Estado	Publicada - 2007
Evento	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brasil Duración: 9 mar 2007 → 11 mar 2007

Serie de la publicación

Nombre	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Conferencia

Conferencia	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
País/Territorio	Brasil
Ciudad	Porto Alegre
Período	9/03/07 → 11/03/07

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10.1109/ISVLSI.2007.3

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Martin-Pirchio, F., Chacón-Rodríguez, A., Julián, P., & Mandolesi, P. (2007). A comparison of low power architectures for digital delay measurement. En Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (pp. 498-499). Artículo 4208971 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures). https://doi.org/10.1109/ISVLSI.2007.3

Martin-Pirchio, Franco ; Chacón-Rodríguez, Alfonso ; Julián, Pedro et al. / A comparison of low power architectures for digital delay measurement. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. 2007. pp. 498-499 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures).

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title = "A comparison of low power architectures for digital delay measurement",

abstract = "Two different versions of a method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz are compared in terms of their power dissipation. Power dissipation simulations are run on both versions from their layout on a 0.35μm technology. The second version shows a cut of 37% in total dissipation under the same test conditions.",

author = "Franco Martin-Pirchio and Alfonso Chac{\'o}n-Rodr{\'i}guez and Pedro Juli{\'a}n and Pablo Mandolesi",

year = "2007",

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Martin-Pirchio, F, Chacón-Rodríguez, A, Julián, P & Mandolesi, P 2007, A comparison of low power architectures for digital delay measurement. En Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures., 4208971, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, pp. 498-499, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07, Porto Alegre, Brasil, 9/03/07. https://doi.org/10.1109/ISVLSI.2007.3

A comparison of low power architectures for digital delay measurement. / Martin-Pirchio, Franco; Chacón-Rodríguez, Alfonso; Julián, Pedro et al.
Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. 2007. p. 498-499 4208971 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

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AB - Two different versions of a method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz are compared in terms of their power dissipation. Power dissipation simulations are run on both versions from their layout on a 0.35μm technology. The second version shows a cut of 37% in total dissipation under the same test conditions.

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Martin-Pirchio F, Chacón-Rodríguez A, Julián P, Mandolesi P. A comparison of low power architectures for digital delay measurement. En Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. 2007. p. 498-499. 4208971. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures). doi: 10.1109/ISVLSI.2007.3

A comparison of low power architectures for digital delay measurement

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