A compact functional verification flow for a RISC-V 32I based core

Roberto Molina-Robles; Edgar Solera-Bolanos; Ronny Garcia-Ramirez; Alfonso Chacon-Rodriguez; Alfredo Arnaud; Renato Rimolo-Donadio

A compact functional verification flow for a RISC-V 32I based core

Roberto Molina-Robles, Edgar Solera-Bolanos, Ronny Garcia-Ramirez, Alfonso Chacon-Rodriguez, Alfredo Arnaud, Renato Rimolo-Donadio

Escuela de Ingeniería Electrónica

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

Idioma original	Inglés
Título de la publicación alojada	2020 Ieee 3rd Conference On Phd Research In Microelectronics And Electronics In Latin America (prime-la)
Número de páginas	4
Estado	Publicada - 2020

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title = "A compact functional verification flow for a RISC-V 32I based core",

keywords = "</bold>, EDA tools, Functional Verification, Risc-v 32i, SystemVerilog, Uvm, Architecture, Compiler, Coverage, Processor, Reference model<bold>, Regression, Simulation, Test generation",

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A compact functional verification flow for a RISC-V 32I based core. / Molina-Robles, Roberto; Solera-Bolanos, Edgar; Garcia-Ramirez, Ronny et al.
2020 Ieee 3rd Conference On Phd Research In Microelectronics And Electronics In Latin America (prime-la). 2020.

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

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T1 - A compact functional verification flow for a RISC-V 32I based core

AU - Molina-Robles, Roberto

AU - Solera-Bolanos, Edgar

AU - Garcia-Ramirez, Ronny

AU - Chacon-Rodriguez, Alfonso

AU - Arnaud, Alfredo

AU - Rimolo-Donadio, Renato

PY - 2020

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KW - Uvm

KW - Architecture

KW - Compiler

KW - Coverage

KW - Processor

KW - Reference model<bold>

KW - Regression

KW - Simulation

KW - Test generation

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M3 - Contribución a la conferencia

BT - 2020 Ieee 3rd Conference On Phd Research In Microelectronics And Electronics In Latin America (prime-la)

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