Performance analysis - A theoretical two latencies model

Fernando Herrera, Felix Njeh, Francisco J. Torres-Rojas

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Recent technological advances requires more sophisticated systems architecture to support the growing demands in performance and power requirements. A key challenge to chip designers, architects, engineers, users and scholars is how to effectively evaluate the performance of a system. In this paper, we present a theoretical model to analyze system performance based on two components: transport and execution latencies. This model was used to analyze the performance on a multithreaded memory bound workload. The results correlate with measurement data collected on an Intel Haswell architecture.

Original languageEnglish
Title of host publicationProceedings - 2018 International Conference on Computational Science and Computational Intelligence, CSCI 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1427-1430
Number of pages4
ISBN (Electronic)9781728113609
DOIs
StatePublished - Dec 2018
Event2018 International Conference on Computational Science and Computational Intelligence, CSCI 2018 - Las Vegas, United States
Duration: 13 Dec 201815 Dec 2018

Publication series

NameProceedings - 2018 International Conference on Computational Science and Computational Intelligence, CSCI 2018

Conference

Conference2018 International Conference on Computational Science and Computational Intelligence, CSCI 2018
Country/TerritoryUnited States
CityLas Vegas
Period13/12/1815/12/18

Keywords

  • Cache hierarchy
  • CPU performance analysis
  • Execution latency
  • Intel haswell
  • Memory latency
  • Top down analysis

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