A comparison of low power architectures for digital delay measurement

Franco Martin-Pirchio, Alfonso Chacón-Rodríguez, Pedro Julián, Pablo Mandolesi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Two different versions of a method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz are compared in terms of their power dissipation. Power dissipation simulations are run on both versions from their layout on a 0.35μm technology. The second version shows a cut of 37% in total dissipation under the same test conditions.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationEmerging VLSI Technologies and Architectures
Pages498-499
Number of pages2
DOIs
StatePublished - 2007
EventIEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil
Duration: 9 Mar 200711 Mar 2007

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Conference

ConferenceIEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Country/TerritoryBrazil
CityPorto Alegre
Period9/03/0711/03/07

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